Analysis of Deep Submicron MOSFET (Metal-Oxide-Semiconductor Field Effect Transistors)
The ability to scale device size while reducing cost is in essence the rationale behind the success of silicon based Integrated Circuits (IC). This research investigates the effects of scaling on IC technology. Two computational tools are used: An advanced Technology Computer Aided Design (TCAD) tool for 2D drift-diffusion simulation and a particle Monte Carlo simulator. Physical analyses are presented using as prototype the MIT Well-tempered MOSFET designs of varying channel length*. Results have shown that as device geometry decreases short channel effects (SCE) such as hot carriers effects, interconnect failures, DIBL (Drain induced Barrier Lowering), mobility degradation, and other reliability issues become predominant. Basic techniques to control SCE are discussed.
School:
University of Illinois at Urbana-Champaign
Department:
Electrical Engineering
Research Advisor:
Umberto Ravaioli
Department of Research Advisor:
Electrical and Computer Engineering
Year of Publication:
2002